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型号 产品描述 RoHS 操作
Cadence Chip Planning System An enterprise-class IC planning and IP reuse environment designed for larger, global organizations n... 立即亚博国际违法吗
Cadence InCyte Chip Estimator Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and c... 立即亚博国际违法吗
Cadence Low-Power Methodology Kit 将低功耗技术流程组成一个有机的系统,并优化其具体应用于。从而通过完整的前端到后端方法学,最佳的实践,... 立即亚博国际违法吗
Encounter Conformal Constraint Designer Automates the validation and refinement of constraints to ensure that timing constraints are valid t... 立即亚博国际违法吗
Encounter Conformal ECO Designer Combines automatic ECO analysis, ECO logic optimization, and design netlist modification with the in... 立即亚博国际违法吗
Encounter Conformal Equivalence Checker Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL t... 立即亚博国际违法吗
Encounter Conformal Low Power Enables the creation and validation of power intent in context of the design. Combines low-power equ... 立即亚博国际违法吗
Encounter DFT Architect Minimizes test development and production costs. Delivers a flexible compression solution plus an in... 立即亚博国际违法吗
Encounter RTL Compiler Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a... 立即亚博国际违法吗
Encounter RTL Compiler with Physical Enables logic designers to account for physical interconnect—-without the need to learn how to do ph... 立即亚博国际违法吗
Encounter Timing System Serves both front-end logic designers looking for high-quality static timing analysis and ease of us... 立即亚博国际违法吗
Encounter True-Time ATPG Automatically generates power- and timing-aware test patterns for small delay defects. Provides defe... 立即亚博国际违法吗
Incisive Design Team Manager Drives verification closure using incrementally developed assertion and test list plans. Captures an... 立即亚博国际违法吗
Incisive Design Team Simulator Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (co... 立即亚博国际违法吗
Incisive Desktop Manager 自动化和指导日常验证任务和结果的可视化。 立即亚博国际违法吗
Incisive Formal Verifier 在验证环境可用之前,通过基于断言的验证进行形式化分析,检查RTL模块设计,来加速设计的收敛 立即亚博国际违法吗
Incisive Verification IP 支持先进的测试平台,事务级的高层次的测试平台,基于断言的形式,模拟和加速模块级验证IP,以及仿真和在线... 立即亚博国际违法吗
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